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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33999 Rev 1.0, 01/2004
Preliminary Information 16-Output Switch with SPI and PWM Control
The 33999 is a 16-output low-side switch with a 24-bit serial input control. It is designed for a variety of applications including inductive, incandescent, and LED loads. The Serial Peripheral Interface (SPI) provides both input control and diagnostic readout. Eight parallel inputs are also provided for direct Pulse Width Modulation (PWM) control of eight dedicated outputs. Additionally, an output-programmable PWM input provides PWM of any combination of outputs. A dedicated reset input provides the ability to clear all internal registers and turn all outputs off. The 33999 directly interfaces with microcontrollers and is compatible with both 3.3 V and 5.0 V CMOS logic levels. The 33999, in effect, serves as a bus expander and buffer with fault management features that reduces the MCU's fault management burden. Features * Designed to Operate 5.0 V < VPWR < 27 V * 24-Bit SPI for Control and Fault reporting, 3.3 V/5.0 V Compatible * Outputs Are Current Limited (0.9 A to 2.5 A) to Drive Incandescent Lamps * Output Voltage Clamp of +50 V During Inductive Switching * On/Off Control of Open Load Detect Current (LED Application) * VPWR Standby Current < 10 A * RDS(ON) of 0.55 at 25C Typical * * * * * Independent Overtemperature Protection Output Selectable for PWM Control Output ON Short-to-VBAT and OFF Short-to-Ground/Open Detection 54-Pin Exposed Pad Package for Thermal Performance Pb-Free Packaging Designated by Suffix Code EK
Simplified Application Diagram 33999 SimplifiedApplication Diagram 33999 Simplified Application Diagram
3.3 V/5.0 V VPWR VBAT
33999
POWER DUAL OCTAL SERIAL SWITCH WITH SERIAL PERIPHERAL INTERFACE I/O
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EK (Pb-FREE) SUFFIX CASE 1390-01 54-LEAD SOICW EXPOSED PAD
ORDERING INFORMATION
Device PC33999EK/R2 Temperature Range (TA) -40C to 125C Package 54 SOICW-EP
33999
VDD MCU SCLK CS MISO MOSI PWM RST SCLK CS SI SO PWM RST PWM0 PWM1 PWM6 PWM7 PWM8 PWM9 PWM14 PWM15 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 GND Solenoid/Relay SOPWR VPWR
LED
Lamp
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 2004
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VPWR VDD Overvoltage Detect OVD VDD RB SFPDB SFL SCLK CSB SI SO CSI CSBI
8 VDD Bias Gate Control OUT0 2 50 V OUT1-OUT15: 3, 6, 7, 21, 22, 25, 26, 29, 30, 33, 34, 48, 49, 52, 53
Voltage Regulator GE OT SF OF
PWM 50 RST 47 CS 23
10 A 25 A 10 A Input Buffers 10 A 10 A Serial D/O Line Driver
To Gates 1 to 15
VRef Open Load Detect Enable ILIMIT 50 A RS
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SCLK 20 SI 32 SO 35 SOPWR 5 PWM0 1 PWM1 4 PWM6 24 PWM7 27 PWM8 28 PWM9 31 PWM14 51 PWM15 54
SPI Interface Logic
Short and Open Circuit Detect Overtemperature Detect
GND Pins: 10-18 37- 40 42- 45
PWM0 10 A PWM1 10 A PWM6 10 A PWM7 10 A PWM8 10 A PWM9 10 A PWM14 10 A PWM15 10 A
From Detectors 1 to 15
Figure 1. 33999 Simplified Internal Block Diagram
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PWM0 OUT0 OUT1 PWM1 SOPWR OUT2 OUT3 VPWR NC GND GND GND GND GND GND GND GND GND NC SCLK OUT4 OUT5
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
PWM15 OUT15 OUT14 PWM14 PWM OUT13 OUT12
RST
PWM6 OUT6 OUT7 PWM7
NC GND GND GND GND NC GND GND GND GND NC SO OUT11 OUT10 SI PWM9 OUT9 OUT8 PWM8
PIN FUNCTION DESCRIPTION
Pin 1, 4, 24, 27, 28, 31, 51, 54 2, 3, 6, 7, 21, 22, 25, 26, 29, 30, 33, 34, 48, 49, 52, 53 5 8 9, 19, 36, 41, 46 10-18, 37-40, 42-45 20 23 32 35 47 50 Pin Name PWM0, PWM1, PWM6-PWM9, PWM14, PWM15 OUT0-OUT15 Formal Name PWMn Input Definition Parallel PWM control Input pins. Allows direct PWM control of eight outputs.
Output 0-Output 15
Low-side driver outputs.
SOPWR VPWR NC GND
SOPWR Supply Pin Battery Input No Connect Ground
Power supply pin to the SO output driver. Battery supply input pin. These pins have no connection. Ground for logic, analog, and power output devices.
SCLK CS SI SO RST PWM
System Clock Chip Select Serial Input Serial Output Reset PWM Control Pin
System Clock for internal shift registers of the 33999. SPI control chip select input pin from MCU to 33999. Serial data input pin to the 33999. Serial data output pin Active low reset input pin. PWM control input pin. Supports PWM on any combination of outputs.
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating VPWR Supply Voltage (Note 1) SPI Interface Logic Supply Voltage (Note 1) SPI Interface Logic Input Voltage (CS, PWM, SI, SO, SCLK, RST, PWMn) (Note 1) Output Drain Voltage Frequency of SPI Operation (Note 2) Output Clamp Energy (Note 3) Symbol VPWR SOPWR VIN VDS Value -1.5 to 50 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 45 6.0 50 Unit V V V V MHz mJ V VESD1 VESD2 TSTG TC TJ PD TSOLDER RJA RJC RJB 2000 200 -55 to 150 -40 to 125 -40 to 150 2.0 260 C C C W C C/W 60 1.2 8.0
fSPI
ECLAMP
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ESD Voltage (Note 4) Human Body Model (Note 5) Machine Model (Note 6) Storage Temperature Operating Case Temperature Operating Junction Temperature Power Dissipation (TA = 25C) (Note 7) Lead Soldering Temperature (Note 8) Thermal Resistance Junction-to-Ambient (Note 9) Junction-to-Case (Note 10) Junction-to-Board Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
Exceeding these limits may cause malfunction or permanent damage to the device. This parameter is guaranteed by design but not production tested. Maximum output clamp energy capability at 150C junction temperature using single non-repetitive pulse method. ESD data is available upon request. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). Maximum power dissipation with no heat sink used. Lead soldering temperature limit is for 10 seconds maximum duration. Not designed of immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Tested per JEDEC test JESD52-2 (single-layer PWB). Tested per JEDEC test JESD51-8 (two-layer PWB).
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 3.1 V SOPWR 5.5 V, 5.0 V VPWR 18 V, -40C TC 125C, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Supply Voltage Range Fully Operational Supply Current All Outputs ON, IOUT = 0.3 A Sleep State Supply Current at RST 0.2 SOPWR and/or SOPWR 0.5 V IPWR(SS) VOV VOV (HYS) VPWR(UV) SOPWR ISOPWR(RSTH) ISOPWR(RSTL) SOPWR(UNVOL) IPWR(ON) - -10 27.5 0.8 - 3.1 100 -10 2.0 4.0 1.0 31.5 1.4 3.2 - - - 2.5 8.0 10 35 2.3 3.5 5.5 500 10 3.0 VPWR(FO) 5.0 - 27 mA V
A
V V V V
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Overvoltage Shutdown Overvoltage Shutdown Hysteresis VPWR Undervoltage Shutdown SPI Interface Logic Supply Voltage SPI Interface Logic Supply Current (RST Pin High) SPI Interface Logic Supply Current (RST Pin Low) SPI Interface Logic Supply Undervoltage Lockout Threshold
A A
V
POWER OUTPUT
Drain-to-Source ON Resistance (IOUT = 0.35 A, VPWR = 13 V) TJ = 125C TJ = 25C TJ = -40C Output Self-Limiting Current Outputs Programmed ON Output Fault Detect Threshold (Note 11) Outputs Programmed OFF Output OFF Open Load Detect Current (Note 12) Outputs Programmed OFF (VPWR = 5.0 V) Outputs Programmed OFF (VPWR = 13 V, 18 V) Output Clamp Voltage 2.0 mA IOUT 200 mA Output Leakage Current SOPWR 2.0 V Overtemperature Shutdown (Outputs OFF) (Note 13) Overtemperature Shutdown Hysteresis (Note 13) TLIM TLIM(hys) IOUT(lkg) -10 155 5.0 2.0 165 10 10 180 20 C C I OCO(5) IOCO(13,18) VCL 45 50 55 25 30 50 50 100 100 V VOUTth(F) 2.5 3.0 3.5 IOUT(lim) 0.9 1.2 2.5 V RDS(ON) - - - 0.75 0.55 0.45 1.2 1.2 1.2 A
A
A
Notes 11. Output Fault Detect Thresholds with outputs programmed OFF. Output Fault Detect Thresholds are the same for output open and shorts. 12. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded to be OFF. 13. This parameter is guaranteed by design but is not production tested.
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions of 3.1 V SOPWR 5.5 V, 5.0 V VPWR 18 V, -40C TC 125C, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic Symbol Min Typ Max Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds (Note 14) Input Logic Voltage Thresholds for RST SI Pull-Down Current SI = 5.0 V
CS Pull-Up Current CS = 0 V
VINLOGIC VINRST ISI
0.8 SOPWR /2- 0.7 2.0
- SOPWR /2 10
2.2 SOPWR /2+0.7 30
V V
A A
-30 -10 10 -2.0
ICS ISCLK 2.0 IRST 5.0 IPWM VSOH SOPWR - 0.4 VSOL - CIN - - - 0.4 20 SOPWR -0.2 - 2.0 25 10 50 30 30
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SCLK Pull-Down Current SCLK = 5.0 V
RST Pull-Down Current RST = 5.0 V
A A A
V
PWM and PWMn Pull-Down Current SO High-State Output Voltage ISO-high = -1.6 mA SO Low-State Output Voltage ISO-low = 1.6 mA Input Capacitance on SCLK, SI, Tri-State SO, RST (Note 15)
V
pF
Notes 14. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, PWM, and PWMn. 15. This parameter is guaranteed by design but is not production tested.
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 3.1 V SOPWR 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT TIMING
Output Slew Rate RL = 56 (Note 16) Output Turn ON Delay Time (Note 17) Output Turn OFF Delay Time (Note 17) Output ON Short Fault Disable Report Delay (Note 18) t DLY(on) t DLY(off) t DLY(short) t DLY(open) t FREQ SR 1.0 1.0 1.0 100 100 - 2.0 15 15 - - - 10 50 50 450 450 2.0 V/s
s s s s
kHz
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Output OFF Open Fault Delay Time (Note 18) Output PWM Frequency
DIGITAL INTERFACE TIMING
Required Low State Duration on VPWR for Reset VPWR 0.2 V (Note 19) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to SI (Required Setup Time) SI, CS, SCLK Signal Rise Time (Note 20) SI, CS, SCLK Signal Fall Time (Note 20) Time from Falling Edge of CS to SO Low Impedance (Note 21) Time from Rising Edge of CS to SO High Impedance (Note 22) Time from Rising Edge of SCLK to SO Data Valid (Note 23) Notes 16. Output slew rate measured across a 56 resistive load.
17. Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage.
t RST - t LEAD t LAG t SI(su) t SI(hold) t r (SI) t f (SI) t SO (en) t SO (dis) t VALID 100 50 16 20 - - - - - - - - - - 5.0 5.0 - - 25 10 - - - - - - 50 50 80
s
ns ns ns ns ns ns ns ns ns
18. 19. 20. 21. 22. 23.
Duration of fault before fault bit is set. Duration between access times must be greater than 450 s to read faults. This parameter is guaranteed by design but is not production tested. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output status data to be terminated at SO pin. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
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Timing Diagram
CS
0.2 VDD
t LEAD 0.7 VDD
t LAG
SCLK
0.2 VDD tSI(su) tSI(hold) MSB IN t VALID 0.7 VDD Don't Care 0.2 V
DD
SI
tSO(en)
0.7 VDD 0.2 VDD
t SO(dis) LSB OUT VTri-State
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SO
MSB OUT
Figure 2. SPI Timing Characteristics
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33999 is designed and developed for automotive and industrial applications. It is a 16-output power switch having 24-bit serial control. The 33999 incorporates SMARTMOS technology having CMOS logic, bipolar/MOS analog circuitry, and independent DMOS power output transistors. Many benefits are realized as a direct result of using this mixed technology. Figure 1, page 2, illustrates a simplified internal block diagram of the 33999.
MCU INTERFACE DESCRIPTION
In operation the 33999 functions as a 16-output serial switch serving as a microcontroller unit (MCU) bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. The 33999 directly interfaces to an MCU, operating at system clock serial frequencies up to 6.0 MHz using a Serial Peripheral Interface (SPI) for control and diagnostic readout. Figure 3 illustrates the basic SPI configuration between an MCU and one 33999. MC68HCXX Microcontroller MCU is clocked daisy chain through each device while the Chip Select bit (CS) is commanded low by the MCU. During each clock cycle, output status from the daisy-chained 33999s is being transferred back to the MCU via the Master In Slave Out (MISO) line. On rising edge of CS, data stored in the input register is then transferred to the output driver. Daisy chain control of the 33999 requires 24 bits per device. MC68HCXX Microcontroller 33999 33999
Shift Register MISO MOSI Shift Register MISO SCLK Receive Buffer Parallel Ports RST CS PWM To Logic SI SO 24-Bit Shift Register Parallel Ports SCLK PWM1 PWM2 MOSI SI SO SCLK CS PWM RST
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33999
SI SO SCLK CS PWM RST
Figure 3. 33999 SPI Interface with Microcontroller All inputs are compatible with 3.3 V/5.0 V CMOS logic levels and incorporate positive logic. An input programmed to a logic low state (< 0.8 V) has the corresponding output OFF. Conversely, an input programmed to a logic high state (> 2.2 V) has the output being controlled ON. Diagnostics is treated in a similar manner--outputs with a fault will feed back (via SO) to the microcontroller a logic [1], while normal operating outputs will provide a logic [0]. The 33999 may be controlled and provide diagnostics using a daisy chain configuration or in parallel mode. Figure 4 shows the daisy chain configuration using the 33999. Data from the
Figure 4. 33999 SPI System Daisy Chain Multiple 33999 devices can be controlled in a parallel input fashion using the SPI. Figure 5, page 10, illustrates potentially 32 loads being controlled by two dedicated parallel MCU ports used for chip select.
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MC68HCXX Microcontroller 33999
MOSI Shift Register MISO SCLK PWM1 PWM2 RST SI SO SCLK CS PWM
Parallel Ports
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33999
SI SO SCLK CS PWM RST
Figure 5. Parallel Inputs SI Control
FUNCTIONAL PIN DESCRIPTION
Chip Select (CS) Pin
The system MCU selects which 33999 is to be communicated with through the use of the Chip Select (CS) pin. When the CS pin is in a logic low state, data can be transferred from the MCU to the 33999 and vise versa. Clocked-in data from the MCU is transferred from the 33999 Shift register and latched into the power outputs on the rising edge of the CS signal. On the falling edge of the CS signal, output fault status information is transferred from the Power Outputs Status register into the device's SO Shift register. The SO pin output driver is enabled when CS is low, allowing information to be transferred from the 33999 to the MCU. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SCLK is in a logic low state. device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal at the SCLK and SI pins is ignored and the SO is tri-stated (high impedance).
Serial Input (SI) Pin
The Serial Input (SI) pin is used to enter one of seven serial instructions into the 33999. SI SPI bits are latched into the Input Shift register on each falling edge of SCLK. The Shift register is full after 24 bits of information are entered. The 33999 operates on the command word on the rising edge of CS. To preserve data integrity, exercise care to not transition SI as the SCLK transitions from high-to-low state (see Figure 2, page 8).
Serial Output (SO) Pin
The Serial Output (SO) pin transfers fault status data from the 33999 to the MCU. The SO pin remains tri-state until the CS pin transitions to a logic low state. All faults on the 33999 are reported to the MCU as logic [1]. Conversely, normal operating outputs with nonfaulted loads are reported as logic [0]. On the falling edge of the CS signal, output fault status information is transferred from the Power Outputs Status register into the device's SO Shift register. The first eight positive transitions of SCLK will provide Any Fault (bit 23), Overvoltage Fault (bit 22), followed by six logic [0]s (bits 21 to 16). The next 16 successive positive clock provides fault status for output 15 to output 0. The SI/SO shifting of data follows a first-in, first-out protocol with
System Clock (SCLK) Pin
The System Clock (SCLK) pin clocks the Internal Shift register of the 33999. The Serial Input (SI) pin accepts data into the Input Shift register on the falling edge of the SCLK signal while the Serial Output (SO) pin shifts data information out of the Shift register on the rising edge of the SCLK signal. False clocking of the Shift register must be avoided to guarantee validity of data. It is essential the SCLK pin be in a logic low state whenever the Chip Select (CS) pin makes any transition. For this reason, it is recommended, though not necessary, that the SCLK pin is commanded to a low logic state as long as the
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both input and output words transferring the Most Significant Bit (MSB) first.
SO Output driver Power Supply (SOPWR) Pin
The SOPWR pin is used to supply power to the 33999 SO output driver and Power-ON Reset (POR) circuit. To achieve low standby current on VPWR supply, power must be removed from the SOPWR pin. The 33999 will be in reset with all drivers OFF when SOPWR is below 2.5 V. The 33999 does not detect overvoltage on the SOPWR supply pin.
protection and shutdown. An overvoltage condition (> 50 s) on the VPWR pin causes the 33999 to shut down all outputs until the overvoltage condition is removed. Upon return to normal input voltage, the outputs respond as programmed by the overvoltage bit in the Global Shutdown/Retry Control register. The overvoltage threshold on the VPWR pin is specified as 27.5 V to 35 V with 1.4 V typical hysteresis. Following an overvoltage shutdown of output drivers, the Overvoltage Fault and the Any Fault bits in the SO bit stream will be logic [1].
Output/Input (OUT0-OUT15) Pins
These pins are low-side output switches controlling the load.
PWM Pin
The PWM Control pin is provided to support PWM of any combination of outputs. Logic for PWM control is provided in the LOGIC OPERATION section (below).
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Reset (RST) Pin
The Reset (RST) pin is the active low reset input pin used to turn OFF all outputs, thereby clearing all internal registers.
Pulse Width Module (PWMn) Pins
PWM0, PWM1, PWM6, PWM7, PWM8, PWM9, PWM14, and PWM15 input pins allow direct PWM control of OUT0, OUT1, OUT6, OUT7, OUT8, OUT9, OUT14, and OUT15, respectively. Logic for PWM control is provided in the LOGIC OPERATION section.
Battery Input (VPWR) Pin
The VPWR pin is used as the input power source for the 33999. The voltage on VPWR is monitored for overvoltage
LOGIC OPERATION Introduction
The 33999 provides flexible control of 16 low-side driver outputs. The device allows PWM and ON/OFF control through the use of several input command words. This section describes the logic operation and command registers of the 33999. The 33999 message set consists of seven messages as shown in Table 1. Bits 23 through 18 determine the specific command and bits 15 through 0 determine how a specific output will operate. The 33999 operates on the command word on the rising edge of CS. Note Upon Power-ON Reset all bits are defined as shown in Table 1.
Table 1. SPI Control Commands
MSB Commands ON/OFF Control Register 0 = off, 1 = on Open Load Current Enable 0 = disable, 1 = enable Global Shutdown/Retry Control 0 = shutdown, 1 = retry SFPD Control 1 = therm only, 0 = VDS PWM Enable 0 = SPI only, 1 = PWM AND/OR Control 0 = PWM pin AND with SPI 1 = PWM pin OR with SPI Reset SO Response 0 = No Fault, 1 = Fault 23 0 0 0 22 0 0 0 21 0 0 0 20 0 0 0 19 0 0 1 18 0 1 0 17 X X Thermal Bit 0 X X X 16 X X Overvoltage 0 X X X 15 0 0 X 14 0 0 X 13 0 0 X 12 0 0 X 11 0 0 X 10 0 0 X 9 0 0 X 8 0 0 X 7 0 0 X 6 0 0 X 5 0 0 X 4 0 0 X 3 0 0 X 2 0 0 X 1 0 0 X LSB 0 0 0 X
0 0 0
0 0 0
0 0 0
0 1 1
1 0 0
1 0 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
0
0
0 0
1 0
1 0
0 0
X 0
X 0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any OverFault voltage
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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ON/OFF Control Register
To program the 16 outputs of the 33999 ON or OFF, a 24-bit serial stream of data is entered into the SI pin. The first 8 bits of the control word are used to identify the on/off command and the remaining 16 bits are used to turn ON or OFF the specific output driver.
are used to identify the PWM enable command, and the remaining 16 bits are used to enable or disable the PWM of the output drivers. A logic [1] in the PWM Enable register allows the user to OR/ AND the PWM input with SPI Control bit and disables the specific parallel control input (PWM0, PWM1, PWM6, PWM7, PWM8, PWM9, PWM14, and PWM15). A logic [0] in the PWM Enable register will disable the PWM to a specific output and allow the user to use the parallel PWM control inputs (PWM0, PWM1, PWM6, PWM7, PWM8, PWM9, PWM14, and PWM15) and the SPI ON/OFF Control bits. Power-ON Reset (POR) or the RST pin or the RESET command will set the PWM enable register to logic[0].
Open Load Current Enable Control Register
The Open Load Enable Control register is provided to enable or disable the 50 A open load detect pull-down current. This feature allows the device to be used in LED applications. Power-ON Reset (POR) or the RST pin or the RESET command disables the 50 A pull-down current. No open load fault will be reported with the pull-down current disabled. For open load to be active, the user must program the Open Load Current Enable Control register with logic [1].
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AND/OR Control Register
The AND/OR Control register describes the condition by which the PWM pin controls the output driver. A logic [0] in the AND/OR Control register will AND the PWM pin with the control bit in the SPI Control register. Likewise, a logic [1] in the AND/ OR Control register will OR the PWM pin with the control bit in the ON/OFF Control register (see Figure 6).
On/Off Control Bit On/Off Control Bit PWM IN AND/OR Control Bit
Global Shutdown/Retry Control Register
The Global Shutdown/Retry Control register allows the user to select the global fault strategy for the outputs. The Overvoltage control bit (bit 16) sets the operation of the outputs when returning from overvoltage. Setting the Overvoltage bit to logic [0] will force all outputs to remain OFF when VPWR returns to normal level. Setting the Overvoltage bit to logic [1] will command outputs to resume their previous state when VPWR returns to normal level. Bit 17 is the global thermal bit. When bit 17 is set to logic [0], all outputs will shut down when thermal limit is reached and remain off even after cooled. With bit 17 set to logic [1], all outputs will shut down when thermal limit is reached and will retry when cooled.
PWM Enable Bit
To Gate Control
On/Off control Bit PWM IN
Short Fault Protect Disable (SFPD) Control Register
All outputs contain a current limit and thermal shutdown with programmable retry. The SFPD control bits are used for fast shutdown of the output when an overcurrent condition is detected but thermal shutdown has not been achieved. The SFPD Control register allows selection of specific outputs for incandescent lamp loads and specific outputs for inductive loads. By programming the specific SFPD bit as logic [1], output will rely on Overtemperature Shutdown only. Programming the specific SFPD bit as logic [0] will shut down the output after 100 s to 450 s during turn on into short circuit. The decision for shutdown is based on output drain-tosource voltage (VDS ) > 2.7 V. This feature is designed to provide protection to loads that experience more than expected currents and require fast shutdown. The 33999 is designed to operate in both modes with full device protection. Figure 6. PWM Control Logic Diagram
Serial Output (SO) Response Register
Fault reporting is accomplished through the SPI interface. All logic [1]s received by the MCU via the SO pin indicate fault. All logic [0]s received by the MCU via the SO pin indicate no fault. All fault bits are cleared on the positive edge of CS. SO bits 15 to 0 represent the fault status of outputs 15 to 0. SO bits 21 to 16 will always return logic [0]. Bit 22 provides overvoltage condition status, and bit 23 is set when any fault is present in the IC. The timing between two write words must be greater than 450 s to allow adequate time to sense and report the proper fault status.
Reset Command
The RESET command turns all outputs OFF and sets all internal registers to their Power-ON Reset state (refer to Table 1).
PWM Enable Register
The PWM Enable register determines the outputs that are PWM controlled. The first 8 bits of the 24 bit SPI message word
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FAULT OPERATION
On each SPI communication, a 24-bit command word is sent to the 33999 and a 24-bit fault word is received from the 33999. The Most Significant Bit (MSB) is sent and received first. Command Register Definition: 0 = Output Command Off 1 = Output Command On SO Definition: 0 = No fault 1 = Fault Table 2. Fault Operation Serial Output (SO) Pin Reports
Overtemperature Overcurrent Fault reported by Serial Output (SO) pin. SO pin reports short-to-battery/supply or overcurrent condition. Not reported. SO pin reports output "OFF" open load condition.
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Output ON Open Load Fault Output OFF Open Load Fault
Device Shutdowns
Overvoltage Total device shutdown at VPWR = 27.5 V to 35 V. Resumes normal operation with proper voltage. Upon recovery all outputs assume previous state or OFF based on the Overvoltage bit in the Global Shutdown/Retry Control register. Only the output experiencing an overtemperature shuts down. Output may auto-retry or remain OFF according to the control bits in the Global Shutdown/Retry Control register. Output will remain in current limit 0.9 A to 2.5 A until thermal limit is reached. When thermal limit is reached, device will enter overtemperature shutdown. Output will operate as programmed in the Global Shutdown/Retry Control register. Fault flag in SO Response word will be set.
Overtemperature Overcurrent
APPLICATIONS Power Consumption
The 33999 is designed with one Sleep mode and one Operational mode. In Sleep mode (SOPWR 2.0 V), the current consumed by the VPWR pin is less than 50 A.To place the 33999 in Sleep mode, turn all outputs OFF and remove power from the SOPWR pin. During normal operation, 500 A is drawn from the SOPWR supply and 8.0 mA from the VPWR supply. Care must be taken when paralleling outputs for inductive loads. The Output Voltage Clamp of the output drivers may not match. One MOSFET output must be capable of the inductive energy from the load turn OFF.
SPI Integrity Check
Checking the integrity of the SPI communication is recommended upon initial power-up of the SOPWR pin. After initial system startup or reset, the MCU writes one 48-bit pattern to the 33999. The first 24 bits read by the MCU is the fault status of the outputs, while the second 24 bits is the first bit pattern sent. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note the second 24 bits the MCU sends to the 33999 are the command bits to program registers or activate outputs on the rising edge of CS.
Paralleling of Outputs
Using MOSFETs as output switches allows the connection of any combination of outputs together. The RDS(ON) of MOSFETs has an inherent positive temperature coefficient providing balanced current sharing between outputs without destructive operation. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON), while the Output Current Limit increases correspondingly. Output OFF Open Load Detect current may increase based on how the Output OFF Open Load Detect is programmed. Paralleling outputs from two or more different IC devices is possible but not recommended.
Output OFF Open Load Fault
An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The Output OFF Open Load Fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Each 33999 output has an internal 50 A pull-down current source. The pull-down current is disabled on power-up and must be enabled for Open Load Detect to function. Once enabled, the 33999 will only shut down the pull-down current in Sleep mode or when disabled via SPI. During output switching, especially with capacitive loads, a false Output OFF Open Load Fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 s to 450 s is incorporated. The duration for which a false fault may be reported is a function of the load impedance, RDS(ON), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer must time out before the fault comparator is enabled to detect a faulted threshold. Once the condition causing the Open Load Fault is removed, the device resumes normal operation. The Open Load Fault, however, will be latched in the output SO Response register for the MCU to read.
Output Voltage Clamp
Each output of the 33999 incorporates an internal voltage clamp to provide fast turn-OFF and transient protection of each output. Each clamp independently limits the drain-to-source voltage to 50 V. The total energy clamped (EJ) can be calculated by multiplying the current area under the current curve (IA) times the clamp voltage (VCL) (see Figure 7). Characterization of the output clamps, using a single pulse non-repetitive method at 0.3 A, indicates the maximum energy to be 50 mJ at 150C junction temperature per output.
Drain-to-Source=Clamp Voltage (V CL 45 V) 50 V) Voltage (VCL = 50 V) Drain Current Drain Current (ID = 0.3 A) (ID = 0.3 A)
Drain-to-Source C lamp
Drain Voltage Drain Voltage
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Clamp Energy Clamp Energy (E(E= I= Ix VCL) ) J A xV
J A CL
Shorted Load Fault
A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or by an output experiencing a current greater than the current limit. Three safety circuits progressively in operation during load short conditions afford system protection: 1. The device's output current is monitored in an analog fashion using a SENSEFET approach and is current limited. 2. With the output in current limit, the drain-to-source voltage increases. By setting the SFPD bit to 0, the output shuts down on VDS > 2.7 V typical after 450 s. 3. The output thermal limit of the device is sensed and, when attained, causes only the specific faulted output to shut down. The device remains OFF until cooled. The device then operates as programmed by the shutdown/ retry bit. The cycle continues until the fault is removed or the command bit instructs the output OFF. All three protection schemes set the Fault Status bit (bit 23 in the SO Response register) to logic [1].
Drain-to-Source ON Drain-to-Source ON Voltage (V Voltage (VDS(O N)) ) DS(ON)
GND GND
Curren t Area (IA )
Time Time
Figure 7. Output Voltage Clamping
Reverse Battery Protection
The 33999 device requires external reverse battery protection on the VPWR pin. All outputs consist of a power MOSFET with an integral substrate diode. During reverse battery condition, current will flow through the load via the substrate diode. Under this circumstance relays may energize and lamps will turn on. If load reverse battery protection is desired, a diode must be placed in series with the load.
Overtemperature Fault
Overtemperature Detect circuits are specifically incorporated for each individual output. The shutdown following an overtemperature condition depends on the control bit set in the Retry/Shutdown Control register. Each independent output shuts down at 155C to 180C. When an output shuts down due to an Overtemperature Fault, no other outputs are affected. The MCU recognizes the fault by a logic [1] in the Fault Status bit (bit 23 in the SO Response register). After the 33999 has cooled below the switch point temperature and 10C hysteresis, the output functions as defined by the retry/shutdown bit 17 in the Global Shutdown/Retry Control register.
Undervoltage Shutdown
An undervoltage SOPWR condition results in the global shutdown of all outputs and reset of all control registers. The undervoltage threshold is between 2.0 V and 3.0 V. An undervoltage condition at the VPWR pin results in an output shutdown and reset. The undervoltage threshold is between 3.2 V and 3.5 V. When VPWR is between 5.0 V and 3.5 V, the output may operate per the command word and the status is reported on SO pin, though this is not guaranteed.
33999 14
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PACKAGE DIMENSIONS
EK (Pb-FREE) SUFFIX 54-LEAD SOICW EXPOSED PAD PLASTIC PACKAGE CASE 1390-01 ISSUE B
10.3 5 7.6 7.4 C 9 B 2.65 2.35
52X 54 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
1
0.65
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PIN 1 INDEX
4 9 B B 18.0 17.8
27
28
5.15
2X 27 TIPS
A
54X
SEATING PLANE
0.3 A B C
0.10 A
A R0.08 MIN C A 8 0 0.9 0.5 SECTION B-B 0.1 0.0 C 0.25
GAUGE PLANE
0MIN
(1.43)
0.30 A B C 4.8 4.3
(0.29) 0.30 0.25 0.38 0.22 0.13
M
BASE METAL
4.8 4.3 0.30 A B C
(0.25)
6
PLATING
A BC
8
SECTION A-A
ROTATED 90 CLOCKWISE
VIEW C-C
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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